Description
The ideal candidate should have experience in high-speed serial links with expertise in the following: Very knowledgeable about and experienced with common high-speed SerDes protocols (e.g., PCIe, USB, UCIe, OIF, etc.) Very knowledgeable in system bring-up of high-speed serial links, lab testing, and defining equipment needs Very knowledgeable in scripting (e.g. python, C, Matlab) for automation of validation efforts. Experience with system level S/W setup is a plus Experience in mixed-signal circuit pre-silicon verification and ability to closely work with circuit design team Knowledge of DFT to aid in the system validation Experience in leading mixed-signal SerDes system validation Experience with silicon bring-up, debug and production ramp Knowledge of SerDes design and architecture including CDR and equalization Knowledge of with Tx/Rx equalization techniques and adaptation Knowledge of link jitter budget for high-speed serial links and key block level requirements Knowledge of ADC based links and equalization techniques Familiarity with PCB design and specifications Strong communication, teamwork and problem solving skills Proven track record of delivering under difficult debug and validation scenarios
Minimum Qualifications
Preferred Qualifications
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